Zixuan Li

Biography

I am currently a first-year M.S. student in the iCAS Lab at Shanghai Jiao Tong University, under the supervision of Prof. Xinfei Guo. I received my B.Eng. degree in Information Engineering from Beijing University of Posts and Telecommunications in 2025.

My research focuses on electronic design automation (EDA), particularly physical design for 2.5D and 3D integrated circuits, including placement and floorplanning optimization.

Research Interests

• Physical Design for 2.5D / 3D ICs
• Machine Learning for EDA

News

• May 2026: Our survey on shift-left methodologies in EDA was accepted by ACM Computing Surveys (CSUR).
• Apr 2026: Selected as a DAC Young Fellow.
• Mar 2026: Our work on rectilinear floorplanning benchmarks was accepted by IEEE Data Descriptions.
• Feb 2026: Our work on early-stage chiplet physical design planning was accepted by DAC 2026.
• Jan 2026: Our work on dataflow optimization in macro placement was accepted by TODAES.
• Sep 2025: Our work on shift-left methodologies in EDA was released on arXiv. We also released a curated repository on GitHub.
• Sep 2025: Joined iCAS Lab, Shanghai Jiao Tong University, as an M.S. student under the supervision of Prof. Xinfei Guo.
• Jun 2025: Graduated from Beijing University of Posts and Telecommunications with a B.Eng. degree in Information Engineering. I am sincerely grateful to Prof. Jianwang Zhai and Prof. Kang Zhao for their invaluable guidance and support.
• Feb 2025: Our paper on symmetry optimization in floorplanning was accepted by ISCAS 2025.
• Dec 2024: Won the Second Prize in the EDA Elite Challenge.

Education

• Shanghai Jiao Tong University, M.S. in Computer Science and Technology, 2025–Present
• Beijing University of Posts and Telecommunications, B.Eng. in Information Engineering, 2021–2025

Research Experience

• SJTU Global College iCAS Lab, Research Intern, 2024–2025
• BUPT Integrated EDA Team, Research Intern, 2023–2025

Publications

* denotes equal contribution, # denotes corresponding author.

• Xinyue Wu*, Zixuan Li*, Fan Hu*, Ting Lin, Xiaotian Zhao, Runxi Wang, Xinfei Guo#, Shift-Left Techniques in Electronic Design Automation: A Survey. ACM Computing Surveys (CSUR), 2026.
• Zixuan Li*, Kanglin Tian*, Fan Hu, Zirui Li, Xinyue Wu, Hengyuan Zhang, Shixin Chen, Jianwang Zhai#, Xinfei Guo#, Kang Zhao, ChiPlanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems. ACM/IEEE Design Automation Conference (DAC), 2026.
• Xiaotian Zhao*, Yingjie Wang*, Zixuan Li, Yongfu Li, Yuanshan Pan, Xinfei Guo#, Descriptor: An EDA Physical Design Rectilinear Floorplan Benchmark Dataset. IEEE Data Descriptions, 2026.
• Xiaotian Zhao, Zixuan Li, Yichen Cai, Jiayin Chen, Yuanshan Pan, Xinfei Guo#, DARE: Enriching Physical Dataflow Awareness for Macro Placement Optimization. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2026.

• Zixuan Li, Kanglin Tian, Jianwang Zhai#, Zirui Li, Kang Zhao, HieRFP: A Hierarchical Recognition Framework and Floorplanning for Reusable Modules. IEEE International Symposium on Circuits and Systems (ISCAS), 2025.
• Zirui Li*, Kanglin Tian*, Jianwang Zhai#, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao, FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs. IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), 2025.

• Zirui Li, Jianwang Zhai#, Zixuan Li, Zhongdong Qi, Kang Zhao, Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing. IEEE International Symposium on Circuits and Systems (ISCAS), 2024.

Awards

• Outstanding Graduate, Beijing University of Posts and Telecommunications, 2025
• Second Prize, EDA Elite Challenge, 2024